Hi, all.
I am study the source code of tri-mode Ethernet MAC by Gao jon. And I
find something strange with the Rx FIFO.
When a packet is received with error either CRC error or Rx FIFO
full error, the Fifo_data_err is set to tell the Rx FIFO not
store the current byte and the byte after it until the end of this
packet.
But the bytes before error found were stored to the Rx FIFO, and this
bytes will not end with a eop signal in the fifo. This will cause
some trouble when host CPU reading a packet using eop signal as a end
of packet identifier.
I am not sure if I am right or I misunderstand the code, will some
help me to check out this problem?
And there is another MAC driver problem, how do CPU know MAC received
a packet with one or more error in it?

Thanks